Common to nearly all computing system platforms is the need for substantial amounts of reliable random-access digital memory. Such memory is often employed to contain software, such as operating system and application software, as well as data utilized by these programs. Further, capacity, speed, and reliability requirements for memory for these platforms continue to become more stringent. In addition, a memory controller is often included as part of the memory system to facilitate computer system access to large memory.
In many systems, such as high-performance desktop computing platforms and network servers, memory requirements have been satisfied primarily by one or more dual in-line memory modules (DIMMs), each of which is populated with several dynamic random-access memory (DRAM) devices. Typically, each DIMM provides one or two “ranks,” or portions of the address range of the memory. Each rank includes a number of DRAMs, with each DRAM providing a predetermined number of bits of each addressable word of the rank. Unfortunately, the increase in capacity delivered by DIMMs has been accompanied with a concomitant increase in the occurrence of data errors, necessitating the use of error correction schemes or algorithms to detect and correct the errors. To facilitate these schemes, each DIMM often provides one or more additional DRAMs beyond what the associated computing system requires for its data requirements to allow the attendant memory controller to store error correction data along with the user data in the DIMM.
Current error correction algorithms are often able to correct data associated with one or more entire DRAMs. In this case, for each word in a rank, the error correction scheme would have the capacity to correct at least all bits of a single DRAM for each word of the rank. Such capability is advantageous since “hard,” or permanent, failures often affect a significant portion of a single DRAM. To this end, the memory controller often implements an error correction algorithm that is optimized for the particular DRAM bit-width being employed in the memory system. For example, DIMMs are often designed to use DRAMs providing thousands of memory locations, with each location providing a bit-width of either four or eight. Presuming an error correction algorithm optimized to correct any DRAM of a system employing eight-bit DRAMs, use of the same error correction algorithm in a memory system using four-bit DRAMs likely would not allow replacement of any two of the DRAMs, unlike an error correction algorithm specifically optimized for four-bit DRAMs. Thus, memory systems are typically designed to align the error correction algorithm employed in the memory controller with the particular DRAM devices utilized in the DIMMs to maximize memory system reliability.
However, correlating the error correction algorithm with the type of DRAM employed produces some limitations. For example, a computing system may be designed to accept two or more types of DIMMs differentiated by DRAM bit-widths. Such a system design may be beneficial over the life of the system, as one type of DIMM may be more desirable over another in terms of pricing and availability at various points in time. Thus, as replacements for failed DIMMs in the system are required, the types of DIMMs employed in any one system may change over time. The same holds true during production of a computing product, as the purchase of one DIMM type may be more attractive than another due to prevailing market conditions. In either case, the option of employing one DIMM type over another would not be available if the memory controller is designed and optimized for DIMMs of a specific DRAM bit-width.